Metal-oxide-semiconductor field-effect transistors (MOSFETs) are common semiconductor device structures widely used in the semiconductor industry for switching, amplification, filtering, and other applications related to both analog and digital electrical signals. Conventional planar MOSFETs include a gate electrode overlying a channel region near an upper surface of a semiconductor substrate and a gate dielectric physically separating the gate electrode from the semiconductor material of the channel region. The channel region and gate electrode are flanked on opposite sides by doped source/drain regions defined in the semiconductor material of the substrate. In operation, biasing the gate electrode creates an electric field in the channel region of the substrate, which inverts a thin portion of the channel to a conductive state underneath the gate dielectric and permits minority carriers to travel through the channel between the source/drain regions.
The semiconductor industry consistently strives to fabricate individual devices with smaller physical dimensions, which is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be fabricated using a given area of semiconductor material and to reduce the unit cost and power consumption. Scaling of device feature sizes also improves performance (e.g., increased switching speed) because charge carriers travel shorter distances in the compact device constructions.
Constructing MOSFETs using semiconductor-on-insulator (SOI) technology offers various advantages over counterpart bulk devices including, but not limited to, higher performance, which in part results from lowered parasitic junction capacitance, absence of latch-up, higher packing density, and low voltage applications. Generally, SOI substrates used in these technologies include a thin active layer of silicon, often referred to as an SOI layer, partitioned into discrete electrically-isolated islands or regions (i.e., SOI regions) used to fabricate devices and a thin buried layer of an insulator, also referred to as a back oxide (BOX), electrically isolating the active layer from the balance of the substrate. The source and drain regions of traditional SOI MOSFETs are formed within the active layer of the SOI substrate. The most common material conventionally used for forming the buried insulator layer of an SOI substrate is silicon dioxide having a dielectric constant in the range of 3.9 to 4.2. Generally, the dielectric constant of conventional or standard materials used in the buried insulator layer ranges from 3.9 to 9.
Scaling SOI MOSFETs presents design challenges to the semiconductor industry. Specifically, as the device channel length of an SOI MOSFET is scaled, the SOI layer thickness and the thickness of the buried insulator layer must also be reduced. As the channel length is shortened, the potential barrier between the source/drain regions is reduced due to modulation by the drain electric field. This effect, which is known as drain induced barrier lowering or DIBL, degrades the sub-threshold swing in deep sub-micron devices. Thinning the buried insulator layer reduces DIBL by suppressing the penetration of the drain field towards the source. In the thinned buried insulator layer, DIBL is reduced because a larger fraction of the drain field lines terminate on the substrate instead of the source. However, thinning the buried insulator layer increases junction capacitance, which slows device performance. Conventional approaches for scaling the channel length in SOI MOSFETs into the deep-submicron range have been unable to adequately balance the competing performance drawbacks of DIBL and junction capacitance.
What is needed, therefore, are design structures for semiconductor device structures that overcome these and other disadvantages of conventional SOI MOSFET semiconductor structures.